1. Technical Field
The present disclosure relates generally to the field of computerized devices, data networks and buses. More particularly, in one exemplary aspect, the present disclosure is directed to reliably detecting and enumerating resources in a resource controller.
2. Description of Related Technology
In a typical computer system, the computer system has various interface connections that are managed by internal controllers. An internal controller may be able to accommodate multiple distinct bus architectures which are routed to one or more physical connectors. However, each of the distinct bus architectures may only support a subset of the internal controller capabilities. For example, in the context of the Universal Serial Bus (USB) protocol standard, USB 3.0 compliant controllers support both so-called “SuperSpeed” operation and USB 2.0 speeds (for backward compatibility). Typical implementations of a USB 3.0 controller have distinct physical connectors for both USB 2.0 and SuperSpeed.
Colloquially, the terms “interface”, “port”, “connector” are fluidly used and may have varying meanings according to context. However, for clarity, as used herein, the term “interface” refers without limitation to a point of logical interaction or signaling interaction between distinct entities. For example, within existing USB controller interfaces, a register determines which “port” of the USB interface is active i.e., whether the interface is operating as a USB 2.0 interface, or a USB 3.0 interface. In some cases, the USB 3.0 port may also sometimes be referred to as a “companion port” to the USB 2.0 port. As used hereinafter, the term “connector” refers without limitation to a physical connection point, bus lines, etc.
Recently, incipient products manufactured by the Assignee hereof support multiple logical interfaces via a single universal USB 2.0/USB 3.0 connector, which is automatically switched internally to an appropriate interface. Within this context, when a so-called USB 3.0 “host” and “peripheral” device are connected, the peripheral device may be detected over both of the USB 3.0 and USB 2.0 bus architectures of the host device's controller. According to extant specifications, the controller must determine which bus architecture to use for enumerating the device within a pre-defined time period.
Unfortunately, it has been empirically observed that common implementations of USB 3.0 peripheral devices may require nearly the full pre-defined time period to provide the necessary information used in determining which bus architecture to use for the peripheral device. Moreover, due to certain hardware implementations (such as is necessary to multiplex both USB 2.0 and USB 3.0 functionality to a single physical connector), in some “worst case” scenarios, a peripheral device may actually exceed the pre-defined time period to identify itself as a USB 3.0 capable device, and may instead be enumerated over the USB 2.0 architecture. Unfortunately, once a peripheral device has been enumerated as a USB 2.0 device, the enumerated peripheral device cannot re-enumerate as a USB 3.0 device. This can directly impact user experience e.g., an incorrectly enumerated USB 3.0 capable device will not have its USB 3.0 related functionalities. For example, a USB Attached SCSI (UAS) device that is enumerated as a USB 2.0 High Speed device will have a data transfer rate of approximately forty (40) megabytes per second (MB)/s, whereas the same device when enumerated as a USB 3.0 Superspeed device may support data transfer rates exceeding four hundred (400) MB/s.
Accordingly, there exists a need to improve upon the inefficiencies associated with these prior art approaches. Specifically, methods and apparatus for reliably detecting and enumerating devices to an appropriate controller bus architecture are needed.